Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A current mirror is a circuit configured to copy a current in one branch of the circuit by controlling the current in another branch of the circuit so that the output current of the circuit may be held constant regardless of whether the load on the circuit changes. The current being copied may be for a DC source or an AC source. Current mirrors find use in a variety of applications, such as power amplification. A amplifier might be configured to receive an RF signal and amplify the power of the RF signal. To accurately reproduce the RF signal with amplified power, the power amplifier may be biased by a current mirror so that the current of the power amplifier remains constant.
FIG. 1 is a simplified schematic of a known current mirror 100. The current mirror includes a bias branch 105 and a power amplifier (PA) core 110. The bias branch 105 includes transistors M1 and M3 in series and the PA core includes transistors M2 and M4 in series. The transistors of the current mirror are MOSFETs. For convenience, transistors M1, M2, M3, and M4 are sometimes referred to herein as M1, M2, M3, and M4, respectively, without the prefix term “transistor.” M1 and M2 are source connected to a power source Vdd with M1 connected to Vdd via a controlled current source 112 and with M2 source connected to Vdd via an inductor 115. The source and gate of M1 are connected to define a gate-source node, which is connected to the gate of M2 to bias M2. A first Vout1 node is disposed between inductor 115 and the source of M2.
M3 and M4 are drain connected to ground with M4 drain connected to ground via an inductor 120. The drain and gate of M3 are connected to define a gate-drain node, which is connected to the gate of M4 to bias M4. A second Vout2 node is disposed between inductor 120 and the drain of M4. M1 and M3 act as a voltage divider for Vdd where the node X between M1 and M3 should be Vdd/2. Similarly M2 and M4 act as a voltage divider where the voltage at node Y should also be Vdd/2. Node Y is the input node for an AC input into the PA core.
For accurate current mapping by current mirror 100, the voltage of node X between M1 and M3 should track the voltage of node Y between M2 and M4. However, the voltage of node X can be indeterminate. The indeterminate nature of the voltage at node X makes node Y to be either more or less than Vdd/2, which effects the current mirroring and thereby effects the linearity range of the PA core.